This invention relates generally to the field of integrated circuits, and more specifically, to improving the output buffer stage of CMOS digital integrated circuits.
Resulting from the continued scaling and shrinking of semiconductor device geometries, which are used to form integrated circuits (also known as "chips"), integrated circuits have progressively become smaller and denser. To facilitate these highly integrated semiconductor circuits, the typical supply voltage of 5 volts has been reduced to a voltage level less than 5 volts, commonly from about 3.3 volts to 3.6 volts. In the future, supply voltages may even be reduced even further to, for example, 2.5 volts.
Often for board-level designs, a mix of integrated circuits is used, where some of the integrated circuits are designed to use a standard 5-volt supply voltage while other integrated circuits are designed to use a reduced-level supply voltage. This poses a problem for the lower voltage integrated circuits: Lower voltage integrated circuits must be able to tolerate overvoltage situations which occur when voltage levels greater than the supply voltage level of that integrated circuit are presented at the pad of that integrated circuit. For example, a 5-volt integrated circuit may be used as input to a 3.3-volt integrated circuit; the 3.3-volt integrated circuit must be able to tolerate a signal input of 5 volts.
This situation frequently occurs on the bidirectional input and output bus of a microprocessor. With high-voltage integrated circuits feeding into low-voltage integrated circuits, the low-voltage integrated circuit may encounter excessive voltage stresses in the thin insulation or oxide layers of some of the semiconductor devices in the circuitry interfacing between the integrated circuits. Furthermore, undesirable current leakage paths are created therein resulting in a power loss and also at times, a serious CMOS latch-up condition, among other issues.
Output buffers have been designed to handle the overvoltage problem; such an output buffer is shown in FIG. 1. Output buffers similar to the one shown in FIG. 1 are described in U.S. Pat. No. 5,151,619 and U.S. Pat. No. 5,160,855.
As shown in FIG. 1, the prior art output buffer comprises a PMOS pull-up transistor 22 with a drain connected to a pad 24 and a source connected to a supply voltage VDD. The gate of PMOS transistor 22 is coupled through a passgate, formed by NMOS transistor 16 and PMOS transistor 17, to a voltage pull-up (VPU) signal 12, generated by a predriver circuit 10. The output buffer of FIG. 1 also has NMOS pull-down transistors 26 and 28 connected in series between pad 24 and another supply voltage, VSS or ground. NMOS transistor 26 has a gate connected to VDD. NMOS transistor 28 has a gate connected to a voltage pull-down (VPD) signal 14, generated by predriver circuit 10. A PMOS tracking transistor 20 is coupled between pad 24 and the gate of PMOS pull-up transistor 22. The gate of PMOS transistor 20 is connected to supply voltage VDD. For passgate transistors 16 and 17, the gate of NMOS transistor 16 is connected to supply voltage VDD and the gate of PMOS transistor 17 is connected to pad 24.
PMOS transistors 17, 20, and 22 have a n-well or substrate connection 30 which is typically a floating n-well connection. This n-well 30 is not directly connected to supply voltage VDD as is typically the case with other PMOS transistors on the integrated circuit. Because of the physical nature of a semiconductor integrated circuit, in practice, a parasitic diode (substrate diode) exists between the floating n-well and pad 24. Therefore, the n-well or substrate of PMOS transistors 17, 20, and 22 need not be physically connected together as shown in FIG. 1; rather each of these transistors may have unconnected floating n-well connections that are effectively. at the same potential, all having a parasitic diode connection to pad 24. In this situation, the n-well or substrate of PMOS transistors 17, 20, and 22 will be effectively electrically, or virtually, connected.
Predriver circuit 10 has two inputs, a signal input and an output enable input. tn operation, predriver circuit 10, responsive to a signal input and an output enable input, generates VPU 12 and VPD 14 signals, which drive PMOS pull-up transistor 22 and NMOS pull-down transistor 28 to provide a proper output signal voltage on pad 24. Generally, an output high voltage level (or logic high) is at about VDD and an output low voltage level (or logic low) is at about VSS. Furthermore, the output buffer of FIG. 1 has two operating states: a normal operation state and a highimpedance state (otherwise known as "tristate"). In the normal operation state, the output enable signal is a logic high while in the high-impedance state, the output enable signal is a logic low.
In the normal operation state, to produce an output high at pad 24, predriver circuit 10 produces a low signal at VPU 12 and a low signal at VPD 14. To produce an output low at pad 24, predriver circuit 10 generates a high signal at VPU 12 and a high signal at VPD 14. To produce a highimpedance (tristate) state at pad 24, predriver circuit 10 generates a high signal at VPU 12 and a low signal at VPD 14.
The output buffer of FIG. 1 solves some of the problems that occur when an overvoltage condition occurs at pad 24. An overvoltage condition occurs when a voltage level greater than the supply voltage VDD is applied at pad 24. When a high voltage is applied at pad 24, PMOS transistor 20 allows the gate of PMOS transistor 22 to track the voltage at pad 24 to prevent a leakage current path from pad 24 through the drain-to-source path of PMOS transistor 22 to supply voltage VDD. In operation, the floating n-well connection 30 for PMOS transistors 17, 20, and 22 helps prevent the occurrence of a latch-up condition. This n-well 30 is not directly connected to supply voltage VDD as is typically the case with other PMOS transistors on the integrated circuit. Since there is a parasitic diode (substrate diode) between pad 24 and the n-well connection 30 of PMOS transistors 17, 20, and 22, the n-well of these transistors will track the pad voltage when a voltage above VDD is applied to the pad. Moreover, the n-well voltage will be about the pad voltage less a threshold voltage of the parasitic diode. This prevents forward biasing the parasitic diode of PMOS transistors 17, 20, and 22, thus preventing the occurrence of a latch-up condition.
However, while the prior art circuit addresses this overvoltage problem of leakage current, it fails to recognize or address a number of other problems, both in overvoltage situations and normal operations. For ease of reference these additional problems will be referred to by number, with the order being of no significance.
Problem 1. The prior art circuit's solution to the leakage current path problem only addresses the situation occurring when the voltage at pad 24 is greater than VDD+.vertline.VTP.vertline.(.vertline.VTP.vertline. is the threshold voltage of PMOS transistor 20 including body effect ). However, a problem of the prior art output buffer occurs when PMOS pull-up transistor 22 tristates after a low-to-high transition at pad 24.
The gateof PMOS transistor 22 can only charge to VDD - VTN (VTN is the threshold voltage of NMOS transistor 16 including body effect) through NMOS transistor 16. Thus, PMOS transistor 22 remains on. If pad 24 is externally driven to some voltage above VDD, but just under VDD +.vertline.VTP.vertline., PMOS transistor 20, whose task is to drive the gate of PMOS transistor 22 to the voltage level at pad 24 when the voltage level at pad 24 exceeds VDD, does not turn on. As a result, the source-to-gate voltage of PMOS transistor 22 is equal to .vertline.VTP.vertline.+ VTN, which causes very serious leakage into the supply voltage VDD through PMOS transistor 22.
A potentially significant problem exists since a large amount of current may be directed into supply voltage VDD from pad 24, especially in cases where the integrated circuit has a large number of bidirectional pads such as in a 64-bit bus microprocessor. Furthermore, significant leakage currents will reduce the life span of an integrated circuit due to hot electrons and the electromigration phenomenon degrading the electrical characteristics of semiconductor devices and other electrical materials on the integrated circuit.